The present invention relates to adders and more particularly relates to adders which are embodied in programmable logic arrays.
The performing of logic in an array of identical circuit elements each located at a unique intersection of an input and output line in a grid of intersecting input and output lines is well known. There are many such arrangements of arrays for performing logic. One of them is called a programmable logic array (PLA). An example of one type of PLA can be seen in Cox et al U.S. Pat. No. 3,987,287. In this PLA input decoders generate minterms and feed them into a first array called a product term generator or an AND array to generate product terms which are functions of the inputs to the decoders. These product terms are fed to a second array called a sums of product terms generator or OR array so as to increase the number of functions that can be performed using these product terms without geometrically increasing the size of the AND array needed to perform these functions. The output of the OR array is fed to latches so that both sequential and combinatorial logic can be performed using this PLA.
The logical function performed by these latches is usually an AND function, as shown in co-pending application Ser. No. 866,689 filed Jan. 3, 1978, entitled, "Programmable Logic Array Adder" now issued into U.S. Pat. No. 4,157,590. However, in certain PLAs the latches perform an Ex-OR function. Pages 3653 to 3655 of the May 1975 issue of the IBM Technical Disclosure Bulletin describe an adder which is embodied in PLAs of this type. While such an adder is useful, it has no advantage over an adder embodied in a programmable logic array in which the latches performed an AND function.